陳寶龍副教授(英)

Highest Degree:

Ph.D. in Electronics Engineering, National Chiao Tung University

TEL：

(07)6011000 Ext:32051 Office: B309

E-mail：

plchen@nkust.edu.tw

Expertise:

VLSI Design FPGA Design Digital Frequency Synthesizers
Random Signal Generation and Applications

Laboratory Website:

https://ccee.nkust.edu.tw/p/412-1054-7501.php?Lang=zh-tw

Pao-Lung Chen

Education:

Ph.D.: Ph.D. in Electronics Engineering, National Chiao Tung University
M.S.: M.S. in Electrical Engineering, Texas A&M University, USA

Experience:

Teaching Assistant, Department of Electrical Engineering, Chung Yuan Christian University
Computer and Communications Research Laboratories, Industrial Technology Research Institute
Holtek Semiconductor Inc.
Teacher, Department of Information Technology, Private Kuang-Fu Senior High School
Instructor, Private Chin Min Institute of Technology
Academic Memberships: IEEE, IEICE, Taiwan Integrated Circuit Design Society

Courses Taught:

Digital Design
Digital Design Laboratory
Digital System Laboratory

Electronic Circuits
Digital Electronic Circuits
Electronic Circuits Laboratory

Research Projects:

A Synthesizable Fractional Frequency Synthesizer with Dynamic Frequency Counting and Scalable Randomization, NSC-104-2221-E327-032, 2015.08.01~2016.07.31, Ministry of Science and Technology, Principal Investigator
A Flying-Adder Frequency Synthesizer with Scalable Randomization, NSC-103-2221-E327-046, 2014.08.01~2015.07.31, National Science Council, Principal Investigator.
An Interpolated Flying-Adder Frequency Synthesizer with Randomly Stored Fractional Carries, NSC-102-2221-E327-041, 2013.08.01~2014.07.31, National Science Council, Principal Investigator.
Design and Study of a Wideband Delay-Locked Loop Based on an Interpolated Flying-Adder, NSC-101-2221-E327-037, 2012.08.01~2013.07.31, National Science Council, Principal Investigator.
Design and Applications of CMOS Active Memristors, NSC-100-2221-E327-025, 2011.08.01~2012.07.31, National Science Council, Principal Investigator.
Design and Study of a High-Resolution All-Digital Frequency Synthesizer Using Chaotic Modulation (II), NSC-99-2221-E0327-047, 2010.08.01~2011.07.31, National Science Council, Principal Investigator.
Design and Study of a High-Resolution All-Digital Frequency Synthesizer Using Chaotic Modulation (I), NSC-98-2221-E0327-037, 2009.08.01~2010.07.31, National Science Council, Principal Investigator.
Design of All-Digital Multiphase Phase-Locked Loop and Delay-Locked Loop IPs for High-Definition Multimedia Digital Transmission Interface Receivers (II), NSC-97-2221-E-327-033, 2008.08.01~2009.07.31, National Science Council, Principal Investigator.
Design of All-Digital Multiphase Phase-Locked Loop and Delay-Locked Loop IPs for High-Definition Multimedia Digital Transmission Interface Receivers (I), NSC-96-2221-E-327-041, 2007.08.01~2008.07.31, National Science Council, Principal Investigator
Principal Investigator, “Design and Study of a High-Multiplication Clock Generator,” Industry-Academia Exchange Project, Chin Min Institute of Technology, Project No. CMIT95-C-01-38, Period: 2006/01/01 ~ 2006/10/31.
Design and Study of a High-Multiplication Clock Generator, 2006.01.01~2006.10.31, Chin Hsiang Feng Enterprise Co., Principal Investigator
Principal Investigator, “Development and Application of a High-Precision Time Conversion Circuit Based on a Digitally Controlled Varactor,” Chin Min Institute of Technology, Project No. CMIT-94-03-01, Period: 2005/01/01 ~ 2005/10/31.
Principal Investigator, “Jitter Analysis and Measurement of an All-Digital Clock Generator,” Chin Min Institute of Technology, Project No. CMC-92-03-13, Period: 2003/01/01 ~ 2003/12/31.
Principal Investigator, “Control IP Design of a Software-Based Digital Phase-Locked Loop,” National Science Council, Project No. NSC-91-2525-E-243-002, Period: 2002/08/01 ~ 2003/07/31.
Principal Investigator, “Integration of Computer-Aided Software for the Department of Electronics,” Chin Min Institute of Technology, Project No. CMC-91-T-03-06, Period: 2002/01/01 ~ 2002/12/31.
Principal Investigator, “Microprocessor-Assisted Clock Multiplier,” Chin Min Institute of Technology, Project No. CMC-91-T-03-02, Period: 2002/01/01 ~ 2002/12/31.

Journal Papers:

Pao-Lung Chen, “A Fully Synthesizable Ultra-N Audio Frequency Multiplier for HDMI Applications,” IEEE, TCAS2, Early Access, Oct. 2019.
Liming Xiu, Pao-Lung Chen, and Yong Han, “A Cost-Effective TAF-DPS Syntonization Scheme of Improving Clock Frequency Accuracy and Long-Term Frequency Stability for Universal Applications”, in Low-Power Circuits for Emerging Applications in Communications, Computing, and Sensing, Chapter 5, CRC Press Taylor & Francis Group, ISBN 978-1-138-58001-5, pp97 ~121, Feb. 2019.
Liming Xiu, Pao-Lung Chen,“A Reconfigurable TAF-DPS Frequency Synthesizer on FPGA Achieving 2 ppb Frequency Granularity and Two-Cycle Switching Speed, ” IEEE Trans. on Industrial Electronics, Vol. 64 No. 2, 2017, pp.1233 ~ 1240, (SCI, IF=6.383)
Pao-Lung Chen, Da-Chen Lee, Wei-Chia Li,“Flying-Adder Freuqnecy Synthesizer with Counter Based Randomization Method, ” IEICE Trans. Electron, EC, Vol. 98 No. 6, 2015, pp.480~489 (SCI)
Pao-Lung Chen, Chun-Chien Tsai, "An Interpolated Flying-Adder-Based Frequency Synthesizer," International Journal of Electrical Engineering, Vol. 2011, P. 1 ~ P. 11 , PID: 871835, Nov. 2011. (EI)
Pao-Lung Chen, “Subtraction Inversion for Delta Path’s Hardware Simplification in MASH Delta-Sigma Modulator,” IEICE Trans. Fundamentals, Vol. E-93A, pp. 2616-2620, Dec. 2010. (SCI/EI)
Pao-Lung Chen, Ching-Che Chung, Jyh-Neng Yang, and Chen-Yi Lee, “Clock Generation with Cascaded Dynamic Frequency Counting Loops for Wide Multiplication Range Applications,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 6, pp. 1275-1285, June 2006. (SCI/EI).
Pao-Lung Chen, Ching-Che Chung and Chen-Yi Lee, “A Portable Digitally-Controlled Oscillator Using Novel Varactors,” IEEE Trans. Circuits and Syst. II, Express Briefs, Vol. 52, No. 5, pp. 233-237, May 2005. (SCI/EI)
Pao-Lung Chen and Chen-Yi Lee, “A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting,” IEICE Trans. Fundamentals, Vol. E-88A, pp. 3554-3563, Dec. 2005. (SCI/EI)
Pao-Lung Chen, Ching-Che Chung and Chen-Yi Lee, “A Novel Digitally-Controlled Varactor for Portable Delay Cell Design,” IEICE Trans. Fundamentals, Vol. E-87A, pp. 3324-3326, Dec. 2004. (SCI/EI)

Conference Papers:

Pao-Lung Chen and Luo-Cheng Zhang, A Study on Vehicle Information and Wireless Impedance Matching, 2017 NKFUST College of Electrical Engineering and Computer Science Faculty-Student R&D Results Symposium, 2017.06
Pao-Lung Chena,, Chih-Hsuan Chang，A Flying-Adder Frequency Synthesizer for FPGA-Based Applications，The international conference on engineering and applied science 2016，2016.02
Pao-Lung Chen and Chia-Nan Chen, A Study on Disconnection and Splicing in Network Cabling Engineering, 2016 NKFUST College of Electrical Engineering and Computer Science Faculty-Student R&D Results Symposium, 2016.06
Pao-Lung Chen，A Low-Cost Carry Look-Ahead Adder for Flying-Adder，ICCE-TW 2016，2016.05
Pao-Lung Chen，An Open-Loop Fractional Divider Based on Direct Phase，ICCE-TW 2016，2016.05
Pao-Lung Chen and Chih-Hsuan Chang, 2016 Conference on Engineering and Applied Science, The International Conference on Engineering and Applied Science 2016, 2016.02
Pao-Lung Chen, Inductorless Chua’s Circuit and Memristor, 2015 2nd International Conference on Information Science and Control Engineering, 2015.04
Pao-Lung Chen and Chen-Hung Wu, A Study on Flying-Adder and LFSR Storage Devices, 2015 NKFUST College of Electrical Engineering and Computer Science Faculty-Student R&D Results Symposium, 2015.05
Pao-Lung Chen, Fractional Carry Randomization Using De Bruijn Sequences, IEEE International Conference on Consumer Electronics-Taiwan, 2015.06
Pao-Lung Chen and Ting-Yao Chen, Randomization of a Digitally Controlled Oscillator Using Storage Devices, IEEE International Conference on Consumer Electronics-Taiwan, 2015.06
Pao-Lung Chen, Fractional Carry Randomization Using De Bruijn Sequences, IEEE International Conference on Consumer Electronics-Taiwan, 2015.06
Pao-Lung Chen and Chen-Hung Wu, A Study on Flying-Adder and LFSR Storage Devices, 2015 NKFUST College of Electrical Engineering and Computer Science Faculty-Student R&D Results Symposium, 2015.05
Pao-Lung Chen and Pai-Wei Kuo, Detection of Pseudo-Random Numbers, 2014 NKFUST College of Electrical Engineering and Computer Science Faculty-Student R&D Results Symposium, 2014.05
Pao-Lung Chen and Tzu-Hsiang Wang, A Multiphase Delay-Locked Loop with Interleaving, 2014 International Conference on Information Science, Electronics and Electrical Engineering (ISEEE 2014), 2014.04
Pao-Lung Chen and Chi-Hsin Cheng, A Fractional Pseudo Random Binary Sequence for Spur Reduction in Flying-Adder Frequency Synthesizer, 2014 International Conference on Information Science, Electronics and Electrical Engineering (ISEEE 2014), 2014.04
Pao-Lung Chen and Pai-Wei Kuo, Detection of Pseudo-Random Numbers, 2014 NKFUST College of Electrical Engineering and Computer Science Faculty-Student R&D Results Symposium, 2014.05
Pao-Lung Chen, A Skip Calibration Algorithm Applied to Multiphase Phase-Locked Loops, IEEE 2013 ICCA Conference on Control and Automation, 2013.06
Pao-Lung Chen and Pao-Lung Chang, Flying-Adder Frequency Synthesizer: FPGA Implementation and Measurement, 2013 NKFUST College of Electrical Engineering and Computer Science Faculty-Student R&D Results Symposium, 2013.05
Pao-Lung Chen and Pai-Sung Lin, A Study on Real-Time Power Consumption of Displays, 2013 NKFUST College of Electrical Engineering and Computer Science Faculty-Student R&D Results Symposium, 2013.05
Pao-Lung Chen and In-Ming Yang, Random Number Estimation Using Matlab, 2012 NKFUST College of Electrical Engineering and Computer Science Faculty-Student R&D Results Symposium, 2012.05
Pao-Lung Chen, Hsin-Yu Yu, Jen-Tai Lo, Ke-Xin Lin，The Measurement and Analysis of Chaotic Music，2012 ICEICE，2012.04
Hsu-Kuang Chang, Yi-Wei Kung, King-Chu Hung, Pao-Lung Chen，XML Information for Efficient Retrieval Service with Complete Path Representation，2012 INTERNATIONAL WORKSHOP ON TECHNOLOGY ENHANCED LEARNING AND LIVING (TELL 2012)，2012.02
Pao-Lung Chen, Ke-Xin Lin，Simulation-Based Analysis and Experimental，FIRA 2011，2011.08
Pao-Lung Chen and Tzu-Hsiang Wang, An All-Digital Multiphase Delay-Locked Loop with Reused Successive Approximation Register, 2011 NKUST College of Electrical Engineering and Computer Science Faculty-Student R&D Results Symposium, pp.54-59, May 2011.
Pao-Lung Chen and Sheng-Hsien Hung, A Wireless Lightning Surge Counter for Power Systems, 2011 NKUST College of Electrical Engineering and Computer Science Faculty-Student R&D Results Symposium, pp.60-65, May 2011.
Pao-Lung Chen, Tzu-Siang Wang, Jyun-Han Ciou, “A Multiphase All-Digital Delay-Locked Loop with Reuse SAR,”2010 IEEE APCCAS, pp, 943-946, Dec. 2010.
Pao-Lung Chen，A Low Power Multiphase All-Digital Phase Locked Loop with Reusing SAR，The First International Conference on Green Circuits and Systems，pp. 695-698, June 2010.
Pao-Lung Chen, Chun-Han Chiu, Tzu-Hsiang Wang, and Chun-Chien Tsai, Successive Approximation Register with Monitoring Count, 2010 Joint Engineering and Technology Research Results Presentation of National University of Kaohsiung and National Kaohsiung First University of Science and Technology, April 2010.
Pao-Lung Chen, Tzu-Hsiang Wang, Chun-Han Chiu, and Chun-Chien Tsai, A Multiphase Self-Calibrated Delay-Locked Loop with Reused Successive Approximation Register, 2010 Joint Engineering and Technology Research Results Presentation of National University of Kaohsiung and National Kaohsiung First University of Science and Technology, April 2010.
Pao-Lung Chen, Chun-Chien Tsai, Chun-Han Chiu, and Tzu-Hsiang Wang, Circuit Design of an Improved Successive-Approximation-Register-Controlled Multiphase Digital Phase-Locked Loop, 2010 Symposium on Electronic Communications and Applications, pp. 12-16, May 2010.
Pao-Lung Chen, Chun-Fu Liu, Tsung-Hsiang Lin , “A Multiphase Digital Controlled Oscillator with DVC Technique” , SASIMI 2009 - THE 15TH WORKSHOP ON SYNTHESIS AND SYSTEM INTEGRATION OF MIXED INFORMATION TECHNOLOGIES , Okinawa, Japan.
Pao-Lung Chen and Yi-Tun Chiu, ”Design and Implementation of an Intelligent Industrial Controller for Wireless Communications in the ISM Band,“ 2009 NKUST College of Electrical Engineering and Computer Science Faculty-Student R&D Results Symposium, 2009.05.
Pao-Lung Chen and Yu-Liang Huang, ”Implementation and Simulation of Chaotic Circuits,“ 2009 NKUST College of Electrical Engineering and Computer Science Faculty-Student R&D Results Symposium, 2009.05.
Pao-Lung Chen，”JITTER SIMULATION AND MEASUREMENT OF AN ALL-DIGITAL CLOCK GENERATOR WITH DYNAMIC FREQUENCY COUNTING LOOP”，2008 IEEE ISCAS，2008.05.
Pao-Lung Chen, Tsung-Hsiang Lin, and Chun-Fu Liu, ”An Improved Multiphase Calibration Technique,“ 2008 NKUST College of Electrical Engineering and Computer Science Faculty-Student R&D Results Symposium, 2008.05
Pao-Lung Chen, ”Simulation and Measurement of Jitter Noise in Dynamic Frequency Counting Loop of All-Digital Clock Generator,“ 2007 NKUST College of Electrical Engineering and Computer Science Faculty R&D Results Symposium, 2007.05
Ching-Che Chung, Pao-Lung Chen, and C.-Y. Lee，An All-Digital Delay-Locked Loop for SDRAM Controller Applications，2006 Symposium on VLSI Design, Automation & Test (VLSI-DAT)，2006.04
Pao-Lung Chen, Ching-Che Chung, and C.-Y. Lee, “An All-Digital PLL with Cascaded Dynamic Phase Average Loop for Wide Multiplication Range Applications,” in Proc. IEEE ISCAS’05, May 2005, pp. 4875-4878.
Pao-Lung Chen, and Chen-Yi Lee, “A Compact Software-Controlled Clock Multiplier for SoC Applications,” in Proc. IEEE 45th MWSCAS, Aug. 2002, pp. I499-I502.
Pao-Lung Chen, Kun-Fu Tseng, Ling-Ling Ho, and Chen-Yi Lee, “A phase Frequency Detector using Novel Resettable D Flip-Flop,” Proc. 2002 VLSI Design/CAD Symposium, Taiwan, Aug. 2002, pp. 240-243.
Pao-Lung Chen, and Chen-Yi Lee, “A Novel Structure for Low Power and High Performance Multimedia Processor,” in Proc. DMS’01, The 2001 International Workshops on Multimedia Technologies, Architecture, and Applications, Sep. 2001, pp. 295 ~ 298.
Pao-Lung Chen, and etc., “A 40 MHz chip for a 64-bit Floating Point Processor,” The fourth conference of VLSI design/CAD, Nan-Tou, Taiwan, Aug. 1993.
Pao-Lung Chen, and Mi Lu, “Parallel Polygonal Approximation by the Width of the Set,” in Proc. of the First IEEE Workshop on Imprecise and Approximate Computation, pp. 93-97, Phoenix, Ariz., Dec. 1992.
Pao-Lung Chen, and Mi Lu, “Computing the Diameter and width of a Set,” in Proc. of the 1991 Science, Engineering and Technology Seminars, ME2, pp. 20-23, Huston, Texas, May 1991.

Domestic Journal Papers:

Pao-Lung Chen and Chih-Ming Lien, “A Low Cost Software-Controlled Clock Multiplier,” Chin Min Journal, No. 6, pp. 33-38, June 2002.
Pao-Lung Chen, Ling-Ling Ho, Jui-Ming Hsieh, and Chih-Ming Lien, “A Method for Improving Performance and Reducing Power in Microprocessor,” Chin Min Journal, No. 5, pp. 49-56, Nov. 2001.
Pao-Lung Chen, Yao-Hsuan Chiang, and Chen-Yi Lee, “A 10/100 Mbps Data Recovery System By Five Phases Sampling,” Chin Min Journal, No. 4, pp. 55-61, Oct. 2000.
Pao-Lung Chen, Hsueh-Hui Chen, Chih-Ming Lien, and Chen-Yi Lee, “An Analysis of Standard Cell Usage in Logic Synthesis,” Chin Min Journal, No. 4, pp. 48-54, Oct. 2000.
Pao-Lung Chen, “Market and Applications of Microcontrollers,” Electronics Monthly, Vol. 3, No. 8, Aug. 1997.
Pao-Lung Chen, “A Study on High-Speed Multipliers,” ITRI Computer and Communications Research Laboratories Research Journal, No. 18, pp. 55-59, March 1995.
Pao-Lung Chen, “A Study on Liquid Crystal Displays for Personal Digital Assistants,” ITRI Computer and Communications Research Laboratories Research Journal, No. 37, pp. 15-19, March 1995.

Patents:

Interpolated Multiplexer, I410142
Pao-Lung Chen, and Chen-Yi Lee, “Instruction Pre-fetch Amount Control with Reading Amount Register Flag Set Based on Pre-Detection of Conditional Branch-Select Instruction,” US patent No. 6842846, Jan. 2005.
Chen-Yi Lee and Pao-Lung Chen, “Phase Frequency Detector with A Narrow Control Pulse,” US patent No. 6831485, Dec. 2004.
Pao-Lung Chen, “A Counter-Based All-Digital Clock Multiplier,” R.O.C. Utility Model Patent No. M241888, August 21, 2004.
Pao-Lung Chen and Chen-Yi Lee, “Microprocessor Instruction Fetch Structure,” R.O.C. Utility Model Patent No. 223914, May 1, 2004.
Chen-Yi Lee and Pao-Lung Chen, “Narrow-Control-Pulse Phase-Frequency Detector,” R.O.C. Invention Patent No. 198721, March 1, 2004.
Pao-Lung Chen, “Address Calculation Method and Device for a Program Counter,” R.O.C. Invention Patent No. 090313, March 17, 1998.
Pao-Lung Chen, “Multiplier/Divider Using Register-Controlled Multiplication and Division,” R.O.C. Utility Model Patent No. 119719, January 2, 1997.

Achievement Video:

Dynamic DC-to-DC Boost Circuit Using Digital Pulse-Width Modulation (PWM)

Copyrights:

Programmable STN LCD Controller, Computer Program, Approval No. 8409963, June 20, 1995.

Technical Reports:

Pao-Lung Chen, Design and Study of a High-Multiplication Clock Generator, Chin Min Institute of Technology, 2006.10.31

Former Graduate Students:

Full-Time Graduate Students

Wei-Chia Li, Academic Year 2013 (Military Service), Study on an All-Digital Phase-Locked Loop with Dynamic Frequency Counting
Da-Chen Lee, Academic Year 2013 (Military Service), Study on Applications of Pseudo-Random Storage
Chi-Hsin Cheng, Academic Year 2012 (King Yuan Electronics), Implementation and Analysis of a Pseudo-Random Storage Architecture Combined with a Flying-Adder Frequency Synthesizer
San-Hsiang Lin, Academic Year 2012 (Compal Electronics), Study on an All-Digital Phase-Locked Loop Using LFSR and Flying-Adder
Jen-Tai Lo, Academic Year 2012 (Compal Electronics), Study on the Integration of Chaotic Circuits
Tian-Yao Hsu, Academic Year 2011 (Portwell Inc.), Implementation of a Flying-Adder Frequency Synthesizer and Calibration Circuit
Tzu-Hsiang Wang, Academic Year 2010 (Compal Electronics), Multiphase Self-Calibrated Delay-Locked Loop with Reused Successive Approximation Register
Chun-Han Chiu, Academic Year 2010 (Avision Inc.), Multiphase All-Digital Phase-Locked Loop with Monitoring Count
Chun-Chien Tsai, Academic Year 2009 (Jorjin Technologies), Interpolated Flying-Adder Frequency Synthesizer
Chun-Fu Liu, Academic Year 2008 (Fitipower Integrated Technology) , Circuit Design of a Multiphase Digital Phase-Locked Loop
Tsung-Hsiang Lin, Academic Year 2008 (Microchip, USA) ,Digitally Controlled Multiphase Delay-Locked Loop Using an Improved Calibration Technique

In-Service Graduate Students

Cheng-Hung Wu, Graduate Institute of Computer and Communication Engineering, Academic Year 2013, Study on Flying-Adder and LFSR Random Storage Devices
Wei-Cheng Li, Graduate Institute of Computer and Communication Engineering, Academic Year 2013,Simulation and Analysis of a Flying-Adder Frequency Synthesizer Combined with LFSR
Fang-Sheng Yang, Graduate Institute of Computer and Communication Engineering, Academic Year 2013, Measurement and Analysis of Buck-Boost Rectifier ICs
Chuan-Tai Huang, Graduate Institute of Computer and Communication Engineering, Academic Year 2013, Measurement and Analysis of a Random-Number-Modulated Digitally Controlled Oscillator
Pai-Wei Kuo, Graduate Institute of Computer and Communication Engineering, Academic Year 2013, Detection of Pseudo-Random Numbers
Ting-Yao Chen, Graduate Institute of Computer and Communication Engineering, Academic Year 2012, Study on LFSR with Random Storage Devices
Pao-Lung Chang, Graduate Institute of Computer and Communication Engineering, Academic Year 2011, Flying-Adder Frequency Synthesizer – FPGA Implementation and Measurement
Wen-Chung Wu, Graduate Institute of Computer and Communication Engineering, Academic Year 2011, Simulation and Analysis of a Flying-Adder-Based Frequency Synthesizer
Shu-Chun Wu, Graduate Institute of Computer and Communication Engineering, Academic Year 2011, Simulation and Analysis of Chaotic Circuits Using Matlab
Pai-Sung Lin, Graduate Institute of Computer and Communication Engineering, Academic Year 2011, Study on Real-Time Power Consumption of Displays
Hsin-Yu Yu, Graduate Institute of Computer and Communication Engineering, Academic Year 2010, Measurement and Analysis of Chaotic Music
Ho-Chin Wang, Graduate Institute of Computer and Communication Engineering, Academic Year 2010, Simulation and Spectrum Analysis of Chaotic Circuits
Ying-Ming Yang, Graduate Institute of Computer and Communication Engineering, Academic Year 2010, Random Number Estimation Using Matlab
Ke-Xin Lin, Graduate Institute of Computer and Communication Engineering, Academic Year 2009, Theory and Simulation Analysis of Chaotic Circuits
Ching-Yun Tsai, Graduate Institute of Computer and Communication Engineering, Academic Year 2009, Study and Discussion on the Design of CMOS Operational Amplifiers
Yu-Liang Huang, Graduate Institute of Computer and Communication Engineering, Academic Year 2008, Implementation and Simulation of Chaotic Circuits
Sheng-Hsien Hung, Graduate Institute of Computer and Communication Engineering, Academic Year 2008, Wireless Transmission Design of a Lightning Surge Counter for Power Systems
Yi-Tun Chiu, Graduate Institute of Computer and Communication Engineering, Academic Year 2007, Design and Implementation of an Intelligent Industrial Controller for Wireless Communications in the ISM Band

Academic Activities:

IEEE International Conference on Consumer Electronic - Taiwan 2016
International conference on Engineering and Applied Science
IEEE International Conference on Consumer Electronics-Taiwan
2015 International Conference on Infromation Science and Control Engineering
2014 International Conference on Information Science, Electronics and Electrical Engineering (ISEEE 2014)
2013 IEEE ICCA Conference on Control and Automation
2011 FIRA, Kaoshiung Taiwan
2010 IEEE APCCAS, Kuala Lumpur, Malaysia
2010 IEEE ICGCS, China
2009 SASIMI, Okinawa, Japan
2008 ISCAS, Seattle, USA
2007 IC Layout Teacher Training Workshop
2006 Symposium on VLSI Design, Automation & Test (VLSI-DAT)
2006 Layout Technology Seminar
2005 ISCAS, Kobe, Japan